This application claims priority from Korean Patent Application No. 2003-49136, filed on Jul. 18, 2003, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.
1. Field of the Invention
This disclosure relates to a semiconductor device, and more particularly, to a programming method of a flash memory device.
2. Description of the Related Art
In general, a flash memory device is a kind of nonvolatile electrically erasable and programmable memory device, which does not have to be refreshed.
The flash memory device can be categorized as either NOR or NAND type. As compared with other nonvolatile memory devices, a NOR type flash memory device performs programming and reading operations at very high speed and thus is attracting more attention from users requiring high-speed devices.
FIG. 1 is a cross-sectional view of a memory cell of a NOR type flash memory device. Referring to FIG. 1, a memory cell 10 includes a p-type substrate 11, an n-type source region 12, an n-type drain region 13, a floating gate 14, and a control gate 15. A channel region 16 is disposed between the source region 12 and the drain region 13. The floating gate 14 is disposed over the channel region 16 and insulated by an insulating film 17. The control gate 15 is disposed over the floating gate 14 and insulated by another insulating film 18.
Programming of the memory cell 10 involves injecting hot electrons from the channel region 16 adjacent to the drain region 13 into the floating gate 14.
Typically, the injection of hot electrons entails a two stage process. In the first stage, the source region 12 and the substrate 11 are grounded. In the second stage, a high voltage (e.g., 10 V) is applied to a control gate electrode Vg, and an appropriate voltage (e.g., 5V –6V) for generating hot electrons is applied to the drain region 13.
This programming of the memory cell 10 allows sufficient negative electric charges to accumulate in the floating gate 14. Thus, negative (−) electric potential of the floating gate 14 leads to an increase in the threshold voltage of the memory cell 10 during a series of reading operations.
Reading operation is implemented by applying an appropriate voltage (e.g., 1 V) to the drain region 13 of the memory cell 10, applying a predetermined voltage (e.g., 4.5 V) to the control gate electrode Vg, and applying 0 V to the source region 12.
During the reading operation, the memory cell 10, having the increased threshold voltage due to the programming, prevents injection of currents from the drain region 13 into the source region 12. That is, the memory cell 10 is in a turn-off state.
As shown in FIG. 2, the threshold voltage Vth—cell of the programmed memory cell 10 is typically in the range from about 6 V to 7 V.
Also, the memory cell 10 is erased through Fowler-Nordheim (F-N) tunneling from the floating gate 14 into the substrate 11. This F-N tunneling is enabled by applying a high negative voltage to the control gate electrode Vg and applying an appropriate positive voltage to the substrate 11.
This erasing method allows negative electric charges to discharge from the floating gate 14 into the substrate (i.e., a bulk region) 11. Thus, the threshold voltage Vth—cell of the erased memory cell is lowered during the reading operation.
In the memory cell 10 having the reduced threshold voltage Vth—cell due to the erasing operation, if a certain voltage is applied to the control gate electrode Vg during the reading operation, a current path from the drain region 13 into the source region 12 is formed. That is, the memory cell 10 is in a turn-on state. As shown in FIG. 2, the threshold voltage Vth—cell of the erased memory cell is typically in the range from about 1 V to 3 V.
The programming and erasing of the memory cell 10 are performed by externally applied commands. After the memory cell 10 is programmed, it is detected whether the threshold voltage Vth—cell of the programmed cell is in the range of a target threshold voltage. If the threshold voltage Vth—cell of the programmed cell does not approximate a target value, the memory cell 10 is programmed again.
Also, if it is detected that the threshold voltage Vth—cell of the erased memory cell 10 deviates from the range of the target threshold voltage, the memory cell 10 is erased again or an over-erase repair method is performed such that the threshold voltage Vth—cell of the erased memory cell 10 is in the range of the target threshold voltage.
Programming the memory cell 10 is time consuming, and, although research has been undertaken to reduce the programming time, no adequate solutions yet exist.
Embodiments of the invention address this and other limitations of the prior art.